Notes on the Text

Part I

1. The objective is to be able to design a circuit from the basis of the published data, and know that it will function as predicted when the prototype is constructed.

目标是能够依据公布的数据设计电路，并知道构建的样机将具有预期的功能。

2. It is all too easy with linear circuits, which appear relatively simple when compared with today's complex logic arrangements, to ignore detailed performance parameters which can drastically reduce the expected performance.

对于线性电路而言，它们与现在的复杂逻辑电路结构相比看起来较为简单，（因而在设计中）太容易忽视具体的性能参数了，这些参数可极大地削弱预期性能。

·本句主要结构：It is easy … to ignore …

·两个which从句分别修饰circuits和parameters。

3. Consider a requirement for an amplifier having a voltage gain of 10 at 50 kHz driving into a 10 kΩ load.

考虑对于一个在50kHz频率上电压增益为10的放大器驱动10kΩ负载时的要求。

4. A common low-cost, internally frequency-compensated op amp is chosen; it has the required bandwidth at a closed-loop gain of 10, and it would seem to meet the bill.

选择一个普通的带有内部频率补偿的低价运放，它在闭环增益为10时具有所要求的带宽，并且看来满足价格要求。

5. But it will only produce a few volts output swing when the data clearly shows that the output should be capable of driving to within two or three volts of the power supply.

但是它只能产生几伏的输出摆幅，然而数据表却清楚地显示输出应该能驱动达到电源的2～3V范围以内（例如供电电压是-10～+10V，则根据数据表输出应能达到-8～+8V或-7～+7V）。

6. How many times has a circuit been designed using typical values, only to find that the circuit does not work because the device used is not typical?

有多少次是根据典型值设计好电路后却发现只是因为使用的器件不典型而不能工作呢？

7. Clearly, if certain performance requirements are mandatory, then worst-case values must be used. In many cases, however, the desirability of a certain defined performance will be a compromise between ease of implementation, degree of importance, and economic considerations.

显然，如果某些性能要求是强制性的，则一定要用最不利情况下的数值。然而在许多情况下，某一规定性能是否可取将在易实现性、重要性、经济性之间进行平衡。

8. Simplicity is of the essence since the low parts count implementation is invariably cheaper and more reliable.

简单极为重要，因为用较少元器件实现（的电路）必然更便宜也更可靠。

·low parts count implementation：采用零件少的实现方案。low count：低的计数，即数量少。parts：零件。

9. As an example of this judgment about worst-case design, consider a low-gain DC transducer amplifier required to amplify 10 mV from a voltage source to produce an output of l V with an accuracy of ±1% over a temperature range of 0～70℃.

作为最不利情况设计的例子，考虑一个低增益直流传感器放大器，要求将电压源输出的10mV信号放大，产生1V的输出，在0～70℃范围内达到±1%的精度。

10. A closed-loop gain change of ±1% implies that the loop gain (as explained later) should change by less than ±100% for a closed-loop gain of 100.

闭环增益±1%的变化意味着环路增益（将在下面说明）的变化在闭环增益为100时应该小于±100%。

11. Many op amp specifications include only typical values for offset voltage drift; this may well be in the order of 5 μV/℃, with an unquoted maximum for any device of 30 μV/℃.

许多运放技术指标仅仅给出补偿电压偏移的典型值，这很可能会在5 μV/℃的数量级，而未给出任何器件可以达到的最大值30 μV/℃。

Part Ⅱ

1. It is simply a set of flip-flops (usually D latches or RS flip-flops) connected together so that the output of one becomes the input of the next, and so on in series.

它就是一组触发器（通常是D锁存器或RS触发器）联在一起，使得其中一个触发器的输出成为下一个的输入，以此形成一串。

2. It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.

它被称为移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器移动一位。

3. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-flop, and the signal which is present at the DATA input is stored is the first flip-flop, etc.

在下一个时钟脉冲的前沿，第一个触发器的内容被存放到第二个触发器中，而在数据输入端的信号则存放在第一个触发器中，以此类推。

4. The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.

触发器的并行加载可以是同步的（即在时钟脉冲到达时发生），或者异步的（不依赖于时钟），取决于移位寄存器的设计。

5. The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for a binary counter, the “power of two” it corresponds to.

触发器以这样的方式相互连接，使得一个触发器的输出成为下一个的时钟，以此类推。这样，触发器在链中的位置决定了它的权重，即对于二进制计数器而言就是它所对应的2的幂。

6. Note that a set of lights attached to Q1, Q2, Q3would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse.

注意，一组接在Q1、Q2、Q3上的灯泡将以二进制（模8）形式显示从第一个脉冲开始已完成的完整时钟脉冲数。

7. Therefore there will be a slight time delay, due to the propagation delay of the flip-flops between the time one flip-flop changes state and the time the next one changes state, i.e., the change of state ripples through the counter, and these counters are therefore called ripple counters.

因此将略有时延，这是由一个触发器改变状态到下一个触发器改变状态之间的传播延迟造成的，即状态的变化像波纹一样传过计数器，因而这些计数器被称为波纹计数器。

8. By the use of preset and clear inputs, and by gating the output of each T flip flop with another logic level using AND gates (say logic 0 for counting down, logic 1 for counting up), then a presetable up-down binary counter can be constructed.

利用预置和清零端，通过用与门将每一个T触发器的输出与另一个逻辑电平做逻辑运算（例如0为向下计数，1为向上计数），则可构成可预置的可逆二进制计数器。

9. The output of one flip-flop is the input to the next; the state changes consequently“ripple through” the flip-flops, requiring a time proportional to the length of the counter.

一个触发器的输出是下一个的输入，因而状态的变化以波动形式通过各个触发器，所需时间与计数器的长度成正比。

10. This can be easily done by noting that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1.

这很容易做到，注意到对于二进制计数器，只要所有前面的数字都是1，任何给定的数字都会改变它的值（从1变为0，或者从0变为1）。

Part Ⅲ

1. Control voltage on the VCO changes the frequency in a direction that reduces the phase difference between the input signal and the local oscillator.

压控振荡器的控制电压使频率朝着减小输入信号与本地振荡器之间相位差的方向改变。

2. When the loop is locked, the control voltage is such that the frequency of the VCO is exactly equal to the average frequency of the input signal.

当锁相环处于锁定状态时，控制电压使得压控振荡器的频率正好等于输入信号频率的平均值。

3. The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.

锁相接收机的作用是重建原信号而尽可能地去除噪声。

4. If the original signal is well behaved (stable in frequency), the local oscillator will need very little information to be able to track, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large.

如果原信号质量好（频率稳定），本地振荡器只需要极少信息就能实现跟踪，此信息可通过长时间的平均得到，从而消除可能很强的噪声。